Typically, a memory device will be coupled to an external control device such as a microprocessor. The microprocessor may be incorporated into a personal computer, a personal digital assistant, a telephone, a camera, or other device requiring a nonvolatile memory. A multitude of devices including PDAs, wireless devices, and cell phones continue to evolve and incorporate new multifunction capabilities. New capabilities include Web access, a digital camera, video, and music storage. To be marketable, these new devices must provide new capabilities at lower costs and in smaller spaces. In addition, nonvolatile memory devices must have higher capacities, improved speed, and improved interface flexibility.
For example, in the cell phone market, previous voice only cell phones utilized approximately 4 to 8 megabytes of memory to store data such as phone numbers, call logs, or messages. Currently, consumers now demand cell phones that are feature-rich. New cell phone devices now include Internet browsing, text messaging, games, Java applications, music, and digital cameras. These exemplary applications have caused an increase in memory requirements. Typically, cell phone manufactures now use 64 to 256 megabytes or more memory to store large amounts of data including pictures and music.
Memory options when designing cell phones are numerous; a conventional memory architecture for a multifunction cell phone may use NOR flash for code storage, PSRAM for workspace, and NAND flash for data storage. Some designers also include SRAM for backup. NAND flash memory currently has the lowest cost per bit, however, NAND flash memory also has a slower random access time compared to other memory types and no capability for byte level programming.
As capacities and costs continue to improve, there are also demands for improved memory performance. U.S. Pat. No. 5,488,711 to Hewitt et al. describes a write cache for reducing the time required to load data into an EEPROM device. A microprocessor may issue a read command to a memory device. Referring to FIG. 1, a typical prior art memory read sequence begins with an external device, such as a microprocessor (not shown), sending a first read command (read cmd1) 302 to a memory device. Following the first read command 302, the microprocessor then sends an address (addr1) 304 for the desired data. Next, there is a read delay (read delay1) 306 and subsequently, upon confirmation that flash is ready with date, the data are serially output (data1) 308 through an input-output circuit to the microprocessor. After the first read sequence has been completed, a second read command (read cmd2) 312 is sent and a second read address (addr2) 314 is sent by the microprocessor to the memory device. After the second read command 312 and address 314 have been sent to the memory device from the microprocessor, there is a second read access delay 316 (read delay2), and serial data output 318 time. A third read command and subsequent steps may follow. Although the architecture in Hewitt may improve the performance of the memory device, further performance increases using different or improved architectures are possible.